This invention relates to a method of manufacturing a highly-integrated CMOS transistor having high reliability.
Recently, further micro-fabrication of a CMOS transistor is required, associated with high integration of an LSI.
Accompanied by the micro-fabrication, problems are involved such as:
1) lowering of a characteristic of the transistor due to short channel effect which is caused by shortened channel length of the transistor; PA0 2) increase in parasitic resistance and contact resistance due to formation of shallow source and drain; and PA0 3) increase in electrode resistance due to micro gate electrode. PA0 1) As shown in FIG. 11, since a thermal treatment to the gate electrode at low temperature depletes the gate electrode, the temperature of the thermal treatment is preferable to set comparatively high (e.g., 900.degree. C.) for activating the gate impurity. As shown in FIG. 12, since the thermal treatment to the gate electrode at low temperature increases a resistance of the gate electrode, the temperature of the thermal treatment is preferable to set also comparatively high for lowering the resistance of the gate electrode. With the thermal treatment at low temperature, the gate electrode is depleted and the resistance of the gate electrode is increased, which causes lowering of the characteristic of the transistor. PA0 2) As shown in FIG. 13, in order to prevent the transistor from short channel effect and declination of punch-through voltage, the thermal treatment to fully activate the impurity in impurity diffusion layers which form a source or a drain and not to decrease an effective channel length of the transistor is required. PA0 3) In case where a P-type impurity such as boron is doped to the gate electrode of a P-channel transistor for forming a P-channel transistor of surface channel type (dual gate transistor), when the temperature of the thermal treatment is high, the P-type impurity tunnels through a gate oxide layer to diffuse in a substrate owing to a large diffusion coefficient of the P-type impurity. This causes change in threshold voltage. PA0 1) prevention of the gate electrode by deactivation of the gate impurity from depletion; PA0 2) prevention of increase in short channel effect and of declination of punch-through voltage due to reduction of the effective channel length; and PA0 3) prevention of impurity of the P-type gate electrode from tunneling through the gate oxide layer.
In order to contemplate a further micro transistor, the above problems should be solved.
Meanwhile, in a manufacturing process, a thermal treatment to a gate electrode and diffusion layers to which N-type or P-type impurities are respectively doped is conducted for activating each element such as the gate electrodes and the N-type and P-type impurity diffusion layers and for planarizing an interposed insulating layer between layers at a latter stage after each element are formed.
In case where the thermal treatment is conducted for activating each element and for planarizing the interposed insulating layer is conducted at a latter stage in the manufacturing process, however, below-mentioned problems arise.
For example, with a typical CMOS transistor of polycide structure in which a high-melting-point metal silicide layer is deposited as a gate electrode on a polycrystalline silicon layer:
As described above, the thermal treatment to each element of the transistor at optimum temperature is a key for satisfying requirements which are contrary to the general condition of the thermal treatment.
Meanwhile, with a conventional gate length (design rule), the thermal treatment at one time involves no problem. However, accompanied by the micro-fabrication of the CMOS transistor, a difference becomes large between suitable temperature of the thermal treatment for each element and that of the thermal treatment at one time.
In order to improve an electrical characteristic of micro CMOS transistor whose channel length is not more than sub-micron and a reliability of micro CMOS transistor, below mentioned difficulties must be overcome.
From now on, associated with micronization of design rule to half-micron or quarter-micron, and micro-fabrication of CMOS transistor, the above difficulties must be overcome.